Computer memories may be classified as either volatile, that is memories that lose their stored information when power is removed, or non-volatile, that is memories that retain their stored information when power is removed. One type of nonvolatile memory uses a ferroelectric dielectric layer within the device. The direction of polarization of these ferroelectric capacitor memory devices, commonly called FeRAM, is used to determine its binary storage state.
FeRAM is considered an ideal memory because of its low power consumption, low operation voltage, high writing speed and high endurance. Traditionally, the ferroelectric capacitor is fabricated before the CMOS interconnect process because ferroelectric materials, such as lead zirconate titanate (PZT) and SrBi2TaO9 (SBT), require high temperature treatment (>600° C.) to crystallize into ferroelectric phases. However, the plasma and hydrogen-containing atmospheres used in CMOS interconnect processes damage the ferroelectric capacitor and decrease the reliability of FeRAM (Takashi Hase, Takehiro Noguchi and Yoichi Miyasaka, “Analysis of The Degradation of PZT and SrBi2TaO9 Thin Films with A Reductive Process,” Integrated Ferroelectric, 16, pp. 29-40, 1997). The COI (Capacitor Over Interconnect) process is attractive because it eliminates the backend process damage to the ferroelectric capacitor. However, since interconnect cannot withstand high temperature required for crystallizing PZT into the perovskite phase, COI can only be implemented if PZT can be crystallized at low temperature. Recently, lower temperature processes have been proposed, such as MOCVD-PZT (S. Kobayashi, K. Amanuma, H. Mori, N. Kasai, Y. Maejima, A. Seike, N. Tanabe, T. Tatsumi, J. Yamada, T. Miwa, H. Koike, H. Hada and Toyoshima, “64 Kbit CMVP FeRAM Macro with Reliable Retention/Imprint Characteristics,” IEDM'00 Tech Digest, pp. 783-786, 2000), or O2 free sputtering (Naoya Inoue, Takeshi Nakura and Yoshihiro Hayashi, “Low Thermal-budget Fabrication of Sputtered-PZT Capacitor on Multilevel Interconnects for Embedded FeRAM”, IEDM'00 Tech Digest, pp. 797-800, 2000), but even these improvements still require processing temperature in the range of 430° C. to 475° C. which is still too high for CMOS interconnect, especially for advanced low k application.
See S. L. Lung, C. L. Liu, et al, “Low Temperature Epitaxial Growth of PZT on Conductive Perovskite LaNiO3 Electrode for Embedded Capacitor-Over-Interconnect (COI) FeRAM Application”, IEDM 01 Tech Digest, pp 275-278, 2001.